This invention relates to field effect transistors, and more particularly, to the shape of the channel region of a field effect transistor and a method of controlling the shape.
The Insulated Gate Field Effect Transistor (IGFET) has become the workhorse of the semiconductor industry. Integrated circuits containing tens of millions of such IGFETs are routinely fabricated. In the design of such integrated circuits, it is necessary to know the characteristics of transistors with various widths and lengths of the channel region. IGFETs with very wide channel regions are typically used when relatively large currents are needed, such as driver transistors used to transmit signals to other devices exterior to the integrated circuit. Narrow channel IGFETS are typically used to transmit signals to a few, closely located transistors within an integrated circuit.
In the design of such integrated circuits it is important that the electrical characteristics of IGFETs with different channel sizes be known, and, if the electrical characteristics, such as threshold voltage, current drive capability, and sub-threshold leakage, are not identical, that the characteristics of transistors with different shape factors at least be quantifiable.
One of the effects which leads to transistors of different channel width having different characteristics is that the transistor characteristic at the edge of the channel may be different than the transistor characteristics at the center of a wide channel. If the channel of the transistor is very wide, the transistor characteristics will be dominated by the characteristics at the center of the channel. If the transistor is of a narrow width, the transistor characteristics may be dominated by the characteristics at the edge of the channel.
One parameter which can have a large influence on transistor characteristics is the magnitude of electric field in the gate insulator at the surface of the semiconductor. This electric field arises from the application of a potential to the gate electrode of the transistor relative to the body of the transistor. In the center of the channel region of a wide channel transistor this electric field is determined by the thickness and dielectric constant of the gate dielectric (insulator), and by the surface doping of the underlying semiconductor material. At the edge of the channel region, however, the shape of the edge of the semiconductor and the shape of the gate electrode, as well as the thickness of the gate dielectric, also influence the electric field at the surface of the semiconductor. In particular, if the edge of the semiconductor has a sharp corner with a small radius of curvature, the electric field for a given value of applied gate potential will be higher at this edge than in the central region of the channel. This can affect the characteristics of the IGFET in several ways.
The higher electric field at the edge of the channel region for a given gate potential can result in a premature turn-on of the IGFET, i.e., current will flow at the edge of the IGFET before current flow begins in the central portion of the IGFET. In effect, the threshold voltage at the edge of the IGFET is lower than that at the center thereof, and the effective threshold voltage of an IGFET is a function of the width of the channel. Deleterious circuit effects can occur when a potential is applied to the gate of a narrow channel IGFET which is of a magnitude sufficient to stop current flow in a wide channel IGFET, but which may be such as to allow significant current flow to take place in a narrow channel IGFET. Such an effect would manifest itself as an apparent increased sub-threshold leakage current in the narrow channel IGFETs used in the circuit.
Physically deleterious effects may also occur if the increase of electric field in the gate insulator at the edge of the channel of the IGFET, for a given applied gate potential, is excessive, and results in the electric field exceeding the maximum allowable electric field to prevent breakdown of the gate insulator material. Such excessive electric field in the gate insulator material may result in reduced reliability of the transistors.
FIG. 1 shows a sectional view of a channel region of a prior art IGFET fabricated in a Shallow Trench Isolation (STI) technology. A silicon island 14, having a channel portion 14b, is formed in a semiconductor body 12, which is typically silicon. Channel portion 14b has a top surface 14bb. Surrounding the island 14 is an insulating region 16 that has a lower surface 16b in contact with portions of the silicon body 12, and has side walls 16c in contact with side walls 14bbb of island 14. A top surface 16a of insulating region 16 is at a level above the top surface 14bb of channel region 14b. Insulating region 16 has been formed using Shallow Trench Isolation (STI) techniques. A gate insulator layer 18 (dielectric layer) having an upper surface 18a is on the upper surface 14bb of the channel region 14b. A gate region 20 lies on the upper surfaces 18a and 16a of the insulating regions 18 and 16, respectively. Gate region 20 overlies and typically extends beyond channel region 14b. The gate region 20 is typically doped polysilicon, but can be a material of greater conductivity, such as aluminum, or a metal silicide, such as tungsten silicide, or a composite layer composed of a metal silicide layer and a layer of polysilicon. The corners 30 of the channel region 14b, defined by the intersection of side walls 14bbb and top surface 14bb, are shown as right angles, with little or no radius of curvature. The sharp corners 30 are characteristic of transistors fabricated using prior art techniques, and lead to higher electric fields in the gate insulator 18 in the vicinity of the sharp corners 30 than in the center 31 of the channel region. Such a transistor will suffer from the deleterious effects described above.
It has been found in the prior art that the radius of the corners 30 may be increased, and the electric fields in the gate insulator 18 in the vicinity of the sharp corners 30 reduced, by increasing the thickness of various sacrificial oxide layers used in the fabrication of the prior art structure shown in FIG. 1. The use of such thicker oxide layers will require an increased xe2x80x9ctime at temperaturexe2x80x9d during the fabrication of the structure, which results in undesirable dopant diffusion. Thus, one achieves the reduction of one deleterious effect, high electric fields in the gate insulator, but at the price of another deleterious effect, increased dopant diffusion.
Other prior art attempts to increase the radius of the corners 30 result in the top surface 14bb of the channel region 14b being non-planar. This can lead to undesirable physical or electrical characteristics of the transistors formed. Still other prior art attempts to increase the radius of the corners 30 result in the formation of shallow trenches in the STI insulating region 16 adjacent to the side walls 14bbb of the silicon island 14. This can lead to undesirable electrical characteristics of the transistors formed, or difficulties in later processing steps.
It is desirable to fabricate the IGFETs in such a manner that as few as possible deleterious effects take place at the edges of the channels thereof, and throughout the complete IGFET structure.
The present invention is directed to an Insulated Gate Field Effect Transistor (IGFET) in which a region of a semiconductor channel region of the IGFET is shaped so as to reduce the electric field in the gate insulator resulting from a given applied gate potential, and to a method for fabricating an IGFET so as to result in the elimination of sharp corners of semiconductor at the edge of the channel region of the IGFET.
Viewed from a first process aspect, the present invention is directed to a method for forming a curved edge on a semiconductor island. The method comprises the step of oxidizing the exposed surface of the silicon, with a supply of oxygen to a portion of said surface being restricted by a structure surrounding the surface of the exposed silicon, to form said curved edge.
Viewed from a second process aspect, the present invention is directed to a method for modifying the shape of a gate insulator region and an underlying edge of a channel region of a field effect transistor so as to provide a curved shape to the silicon at the edges of the channel region. The method comprises the steps of: forming on the surface of a silicon body a layer of silicon oxide covered by a layer of silicon nitride; patterning the silicon nitride to form regions where transistors will be formed; etching exposed portions of silicon oxide and the underlying silicon, leaving at least one raised island of silicon with a layer of silicon oxide and a layer of silicon nitride on the surface of the silicon where the transistor is to be formed; etching the semiconductor body to remove the silicon oxide layer under the silicon nitride layer at the periphery of the silicon island to leave a lip of silicon nitride which, in subsequent steps, restricts the access of oxygen to the underlying silicon surface; oxidizing the semiconductor body to form a layer of silicon oxide on the surface of exposed silicon, said layer of silicon dioxide extending underneath the periphery of said silicon nitride, wherein said oxidation of exposed silicon occurs more rapidly at the exposed corners of the silicon island and results in a rounding of said corners; and etching the silicon nitride layer to recess it away from the edge of the channel region.
Viewed from a third process aspect, the present invention is directed to a method of forming a semiconductor island having a top surface and side walls with an intersection of the top surface and the side walls being a curved surface. The method comprises the steps of: forming over the top surface of the semiconductor island a layer of material which leaves a gap between same and a peripheral portion of the top surface near the intersection of the top surface and the side walls so as to restrict oxygen flow into this portion of the top surface; and oxidizing all exposed portions of the semiconductor island so as to create a curved surface at an intersection of the side walls and the top surface thereof.
Viewed from a fourth process aspect, the present invention is directed to a method of forming a semiconductor island having a top surface and side walls with an intersection of the top surface and the side walls being a curved surface. The method comprises the steps of: forming over the top surface of the semiconductor island a layer of material which has a T-like shape with the periphery of the top surface near the intersection of the top surface and the side walls being separated from a top portion of the T-like shaped material so as to restrict oxygen flow into this portion of the top surface; oxidizing all exposed surfaces of the semiconductor island so as to create a curved surface at an intersection of the side walls and the top surface thereof; and etching the silicon nitride layer to recess it away from the edge of the channel region.
Viewed from a fifth process aspect, the present invention is directed to a method of forming a semiconductor island having a top surface and side walls with an intersection of the top surface and the side walls being a curved surface. The method comprises the steps of: forming a silicon oxide layer over the top surface of the semiconductor island; covering said oxide layer with layer of silicon nitride; removing a portion of the silicon oxide layer around the periphery of the top surface of the semiconductor island to leave a gap between the silicon nitride layer and a portion of the top surface of the semiconductor island; oxidizing all exposed portions of the semiconductor island so as to create a curved surface at an intersection of the side walls and the top surface thereof; and etching the silicon nitride layer to recess it away from the edge of the channel region.
Viewed from a sixth process aspect, the present invention is directed to a method of forming a portion of each of a plurality of field effect transistors on a silicon body with the transistors being electrically isolated from each other by shallow trench isolation, each transistor being formed in and on an island of silicon having a top surface and side walls. The method comprises the steps of: forming a silicon oxide layer over the top surface of each island; covering each oxide layer with a layer of silicon nitride; removing a portion of the silicon oxide layer around the periphery of the top surface of the silicon island to leave a gap between the silicon nitride layer and a portion of the top surface of the silicon island; oxidizing all exposed portions of the silicon island so as to round corners of the silicon island at an intersection of the side walls and the top surface thereof; and etching the silicon nitride layer to recess it away from the edge of the channel region.
The invention will be better understood from the following more detailed description in conjunction with the accompanying drawing and claims.